15 Mar
2025
15 Mar
'25
9:17 p.m.
Hi Folks,
On 3/15/25 17:15, Michael Clark wrote:
here is an idea expressed as a simple proof-of-concept
simulator.
- https://github.com/michaeljclark/glyph/
I have been working on a proof-of-concept simulator for a RISC
architecture with an immediate base register next to the program counter
to split the front-end stream into independent instruction and constant
streams. I named it glyph. it features a super-regular encoding scheme
designed for vectorized decoding, and it uses a _i32x2_ vector of
relative displacements in the link register to branch both instructions
and constants at the same time. this evolved from thinking about a
"virt" machine that was good for software to decode but could
potentially be hardware.
I have improved the introductory text, made the 16-bit compressed
instruction table easier to digest, added some test cases, and made
several minor changes to the initial 16-bit instruction encoding.
- change instructions to use simm/uimm for signed and unsigned
immediate and updated the formats in the opcode listing.
- use unsigned immediate on all opcodes except j, b, li, addi.
- change srli, srai, slli to use uimm6 and update in-place.
- remove byte load and store on the basis that compressed
opcodes are used for prolog/epilog spill reload and calls.
- add addib.i64 and subib.i64 instructions using constants.
- jiggle the instructions around so that add/sub, load/store
have similar bit patterns for the ib64(uimm3) variants.
- added mov instruction, renamed pop to popc and reordered.
Michael.